Chatterjee, Krishnendu, et al. “Faster Algorithms for Quantitative Verification in Bounded Treewidth Graphs.”10.1007/s10703-021-00373-5__Formal Methods in System Design, vol. 57, Springer, 2021, pp. 401–28, doi:10.1007/s10703-021-00373-5.

Henzinger, Thomas A., et al. “From Pre-Historic to Post-Modern Symbolic Model Checking.”10.1023/A:1026228213080__Formal Methods in System Design, vol. 23, no. 3, Springer, 2003, pp. 303–27, doi:10.1023/A:1026228213080.

Alur, Rajeev, et al. “Partial-Order Reduction in Symbolic State-Space Exploration.”10.1023/A:1008767206905__Formal Methods in System Design, vol. 18, no. 2, Springer, 2001, pp. 97–116, doi:10.1023/A:1008767206905.

Alur, Rajeev, and Thomas A. Henzinger. “Reactive Modules.”10.1023/A:1008739929481__Formal Methods in System Design, vol. 15, no. 1, Springer, 1999, pp. 7–48, doi:10.1023/A:1008739929481.

Alur, Rajeev, et al. “Computing Accumulated Delays in Real-Time Systems.”10.1023/A:1008626013578__Formal Methods in System Design, vol. 11, no. 2, Springer, 1997, pp. 137–56, doi:10.1023/A:1008626013578.