Bartocci E, Ferrere T, Henzinger TA, Nickovic D, Da Costa AO. 2022. Flavors of sequential information flow. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). VMCAI: Verifcation, Model Checking, and Abstract Interpretation, LNCS, vol. 13182, 1–19.
LibreCat: https://research-explorer.ista.ac.at/record/10774
DOI: 10.1007/978-3-030-94583-1_1
arXiv: 2105.02013

Bartocci E, Ferrere T, Henzinger TA, Nickovic D, Da Costa AO. 2022. Information-flow interfaces. Fundamental Approaches to Software Engineering. FASE: Fundamental Approaches to Software Engineering, LNCS, vol. 13241, 3–22.
LibreCat: https://research-explorer.ista.ac.at/record/11355
DOI: 10.1007/978-3-030-99429-7_1
WoS: 000782393600001

Ferrere T, Henzinger TA, Kragl B. 2020. Monitoring event frequencies. 28th EACSL Annual Conference on Computer Science Logic. CSL: Computer Science Logic, LIPIcs, vol. 152, 20.
LibreCat: https://research-explorer.ista.ac.at/record/7348
DOI: 10.4230/LIPIcs.CSL.2020.20
arXiv: 1910.06097

Nickovic D, Lebeltel O, Maler O, Ferrere T, Ulus D. 2020. AMT 2.0: Qualitative and quantitative trace analysis with extended signal temporal logic. International Journal on Software Tools for Technology Transfer. 22(6), 741–758.
LibreCat: https://research-explorer.ista.ac.at/record/10861
DOI: 10.1007/s10009-020-00582-z
WoS: 000555398600001

Ferrere T, Nickovic D, Donzé A, Ito H, Kapinski J. 2019. Interface-aware signal temporal logic. Proceedings of the 2019 22nd ACM International Conference on Hybrid Systems: Computation and Control. HSCC: Hybrid Systems Computation and Control, 57–66.
LibreCat: https://research-explorer.ista.ac.at/record/6428
DOI: 10.1145/3302504.3311800
WoS: 000516713900007

Ferrere T, Maler O, Nidkovi D, Pnueli A. 2019. From real-time logic to timed automata. Journal of the ACM. 66(3), 19.
LibreCat: https://research-explorer.ista.ac.at/record/7109
DOI: 10.1145/3286976
WoS: 000495406300005

Nidkovi D, Qin X, Ferrere T, Mateis C, Deshmukh J. 2019. Shape expressions for specifying and extracting signal features. 19th International Conference on Runtime Verification. RV: Runtime Verification, LNCS, vol. 11757, 292–309.
LibreCat: https://research-explorer.ista.ac.at/record/7159
DOI: 10.1007/978-3-030-32079-9_17
WoS: 000570006300017

Ferrere T, Maler O, Nickovic D. 2019. Mixed-time signal temporal logic. 17th International Conference on Formal Modeling and Analysis of Timed Systems. FORMATS: Formal Modeling and Anaysis of Timed Systems, LNCS, vol. 11750, 59–75.
LibreCat: https://research-explorer.ista.ac.at/record/7232
DOI: 10.1007/978-3-030-29662-9_4
WoS: 000611677700004

Nickovic D, Lebeltel O, Maler O, Ferrere T, Ulus D. 2018. AMT 2.0: Qualitative and quantitative trace analysis with extended signal temporal logic. TACAS: Tools and Algorithms for the Construction and Analysis of Systems, LNCS, vol. 10806, 303–319.
LibreCat: https://research-explorer.ista.ac.at/record/299
DOI: 10.1007/978-3-319-89963-3_18
WoS: 00445822600018

Ferrere T, Henzinger TA, Saraç E. 2018. A theory of register monitors. LICS: Logic in Computer Science, ACM/IEEE Symposium on Logic in Computer Science, vol. Part 8033, 394–403.
LibreCat: https://research-explorer.ista.ac.at/record/144
DOI: 10.1145/3209108.3209194
WoS: 000545262800041

Bakhirkin A, Ferrere T, Maler O. 2018. Efficient parametric identification for STL. Proceedings of the 21st International Conference on Hybrid Systems. HSCC: Hybrid Systems: Computation and Control, HSCC Proceedings, , 177–186.
LibreCat: https://research-explorer.ista.ac.at/record/182
DOI: 10.1145/3178126.3178132
WoS: 000474781600020

Bartocci E, Ferrere T, Manjunath N, Nickovic D. 2018. Localizing faults in simulink/stateflow models with STL. HSCC: Hybrid Systems: Computation and Control, HSCC Proceedings, , 197–206.
LibreCat: https://research-explorer.ista.ac.at/record/183
DOI: 10.1145/3178126.3178131
WoS: 000474781600022

Elgyütt A, Ferrere T, Henzinger TA. 2018. Monitoring temporal logic with clock variables. FORMATS: Formal Modeling and Analysis of Timed Systems, LNCS, vol. 11022, 53–70.
LibreCat: https://research-explorer.ista.ac.at/record/81
DOI: 10.1007/978-3-030-00151-3_4
WoS: 000884993200004

Bakhirkin A, Ferrere T, Nickovic D, Maler O, Asarin E. 2018. Online timed pattern matching using automata. FORMATS: Formal Modeling and Analysis of Timed Systems, LNCS, vol. 11022, 215–232.
LibreCat: https://research-explorer.ista.ac.at/record/78
DOI: 10.1007/978-3-030-00151-3_13
WoS: 000884993200013

Ferrere T. 2018. The compound interest in relaxing punctuality. FM: International Symposium on Formal Methods, LNCS, vol. 10951, 147–164.
LibreCat: https://research-explorer.ista.ac.at/record/156
DOI: 10.1007/978-3-319-95582-7_9
WoS: 000489765800009

Bakhirkin A, Ferrere T, Henzinger TA, Nickovicl D. 2018. Keynote: The first-order logic of signals. 2018 International Conference on Embedded Software. EMSOFT: International Conference on Embedded Software, 1–10.
LibreCat: https://research-explorer.ista.ac.at/record/5959
DOI: 10.1109/emsoft.2018.8537203
WoS: 000492828500005

Bakhirkin A, Ferrere T, Maler O, Ulus D. 2017. On the quantitative semantics of regular expressions over real-valued signals. FORMATS: Formal Modelling and Analysis of Timed Systems, LNCS, vol. 10419, 189–206.
LibreCat: https://research-explorer.ista.ac.at/record/636
DOI: 10.1007/978-3-319-65765-3_11