DOI,IST REx ID,Research Group,Title of publication
10.1145/3209108.3209194,144,ToHe,A theory of register monitors
10.1007/978-3-319-95582-7_9,156,ToHe,The compound interest in relaxing punctuality
10.1007/978-3-319-96145-3_5,160,ToHe,Layered Concurrent Programs
10.1561/1000000053,5677,ToHe,Contracts for system design
10.1007/978-3-030-04612-5_2,5788,ToHe,Infinite-duration poorman-bidding games
10.1109/emsoft.2018.8537203,5959,ToHe,Keynote: The first-order logic of signals
10.1007/978-3-319-10575-8_1,60,ToHe,Introduction to model checking
10.4230/LIPICS.MFCS.2018.23,6005,ToHe,Timed network games with clocks
10.3390/g9030039,6006,ToHe,An abstraction-refinement methodology for reasoning about network games
10.1016/j.tcs.2017.11.001,608,ToHe,Synthesis from component libraries with costs
10.1007/978-3-030-00151-3_13,78,ToHe,Online timed pattern matching using automata
10.1007/978-3-319-99154-2_4,79,"KrCh,ToHe",Parameter-independent strategies for pMDPs via POMDPs
10.1007/978-3-030-00151-3_4,81,ToHe,Monitoring temporal logic with clock variables
10.1007/978-3-319-95246-8_9,86,"KrCh,ToHe",Computing average response time
10.1007/978-3-319-10575-8,3300,ToHe,Handbook of Model Checking
10.1109/TITS.2017.2778077,434,ToHe,Safety-assured model-driven design of the multifunction vehicle bus controller
10.1145/3178126.3178132,182,ToHe,Efficient parametric identification for STL
10.1145/3178126.3178131,183,ToHe,Localizing faults in simulink/stateflow models with STL
10.1007/978-3-662-54580-5_10,1116,ToHe,Computing scores of forwarding schemes in switched networks with probabilistic faults
10.15479/AT:ISTA:TH_730,1155,ToHe,Statistical and logical methods for property checking