{"conference":{"location":"Pittsburgh, PA, USA","end_date":"2016-10-07","name":"EMSOFT: Embedded Software ","start_date":"2016-10-01"},"publication":"Proceedings of the 13th International Conference on Embedded Software ","day":"01","publication_status":"published","date_published":"2016-10-01T00:00:00Z","project":[{"name":"Quantitative Reactive Modeling","_id":"25EE3708-B435-11E9-9278-68D0E5697425","call_identifier":"FP7","grant_number":"267989"},{"name":"Rigorous Systems Engineering","_id":"25832EC2-B435-11E9-9278-68D0E5697425","call_identifier":"FWF","grant_number":"S 11407_N23"},{"name":"The Wittgenstein Prize","_id":"25F42A32-B435-11E9-9278-68D0E5697425","call_identifier":"FWF","grant_number":"Z211"}],"_id":"1135","doi":"10.1145/2968478.2968499","author":[{"full_name":"Avni, Guy","last_name":"Avni","orcid":"0000-0001-5588-8287","id":"463C8BC2-F248-11E8-B48F-1D18A9856A87","first_name":"Guy"},{"full_name":"Guha, Shibashis","last_name":"Guha","first_name":"Shibashis"},{"first_name":"Guillermo","full_name":"Rodríguez Navas, Guillermo","last_name":"Rodríguez Navas"}],"oa":1,"pubrep_id":"644","quality_controlled":"1","language":[{"iso":"eng"}],"publist_id":"6223","file":[{"date_updated":"2018-12-12T10:09:31Z","file_size":279240,"content_type":"application/pdf","creator":"system","file_id":"4755","date_created":"2018-12-12T10:09:31Z","access_level":"open_access","relation":"main_file","file_name":"IST-2016-644-v1+1_emsoft-no-format.pdf"}],"file_date_updated":"2018-12-12T10:09:31Z","user_id":"3E5EF7F0-F248-11E8-B48F-1D18A9856A87","type":"conference","citation":{"ieee":"G. Avni, S. Guha, and G. Rodríguez Navas, “Synthesizing time triggered schedules for switched networks with faulty links,” in <i>Proceedings of the 13th International Conference on Embedded Software </i>, Pittsburgh, PA, USA, 2016.","ama":"Avni G, Guha S, Rodríguez Navas G. Synthesizing time triggered schedules for switched networks with faulty links. In: <i>Proceedings of the 13th International Conference on Embedded Software </i>. ACM; 2016. doi:<a href=\"https://doi.org/10.1145/2968478.2968499\">10.1145/2968478.2968499</a>","ista":"Avni G, Guha S, Rodríguez Navas G. 2016. Synthesizing time triggered schedules for switched networks with faulty links. Proceedings of the 13th International Conference on Embedded Software . EMSOFT: Embedded Software , 26.","short":"G. Avni, S. Guha, G. Rodríguez Navas, in:, Proceedings of the 13th International Conference on Embedded Software , ACM, 2016.","mla":"Avni, Guy, et al. “Synthesizing Time Triggered Schedules for Switched Networks with Faulty Links.” <i>Proceedings of the 13th International Conference on Embedded Software </i>, 26, ACM, 2016, doi:<a href=\"https://doi.org/10.1145/2968478.2968499\">10.1145/2968478.2968499</a>.","chicago":"Avni, Guy, Shibashis Guha, and Guillermo Rodríguez Navas. “Synthesizing Time Triggered Schedules for Switched Networks with Faulty Links.” In <i>Proceedings of the 13th International Conference on Embedded Software </i>. ACM, 2016. <a href=\"https://doi.org/10.1145/2968478.2968499\">https://doi.org/10.1145/2968478.2968499</a>.","apa":"Avni, G., Guha, S., &#38; Rodríguez Navas, G. (2016). Synthesizing time triggered schedules for switched networks with faulty links. In <i>Proceedings of the 13th International Conference on Embedded Software </i>. Pittsburgh, PA, USA: ACM. <a href=\"https://doi.org/10.1145/2968478.2968499\">https://doi.org/10.1145/2968478.2968499</a>"},"has_accepted_license":"1","date_created":"2018-12-11T11:50:20Z","article_number":"26","scopus_import":1,"title":"Synthesizing time triggered schedules for switched networks with faulty links","month":"10","date_updated":"2021-01-12T06:48:33Z","ddc":["000"],"year":"2016","abstract":[{"lang":"eng","text":"Time-triggered (TT) switched networks are a deterministic communication infrastructure used by real-time distributed embedded systems. These networks rely on the notion of globally discretized time (i.e. time slots) and a static TT schedule that prescribes which message is sent through which link at every time slot, such that all messages reach their destination before a global timeout. These schedules are generated offline, assuming a static network with fault-free links, and entrusting all error-handling functions to the end user. Assuming the network is static is an over-optimistic view, and indeed links tend to fail in practice. We study synthesis of TT schedules on a network in which links fail over time and we assume the switches run a very simple error-recovery protocol once they detect a crashed link. We address the problem of finding a pk; qresistant schedule; namely, one that, assuming the switches run a fixed error-recovery protocol, guarantees that the number of messages that arrive at their destination by the timeout is at least no matter what sequence of at most k links fail. Thus, we maintain the simplicity of the switches while giving a guarantee on the number of messages that meet the timeout. We show how a pk; q-resistant schedule can be obtained using a CEGAR-like approach: find a schedule, decide whether it is pk; q-resistant, and if it is not, use the witnessing fault sequence to generate a constraint that is added to the program. The newly added constraint disallows the schedule to be regenerated in a future iteration while also eliminating several other schedules that are not pk; q-resistant. We illustrate the applicability of our approach using an SMT-based implementation. © 2016 ACM."}],"publisher":"ACM","ec_funded":1,"status":"public","department":[{"_id":"ToHe"}],"oa_version":"Submitted Version"}