--- res: bibo_abstract: - Simulink is widely used for model driven development (MDD) of industrial software systems. Typically, the Simulink based development is initiated from Stateflow modeling, followed by simulation, validation and code generation mapped to physical execution platforms. However, recent industrial trends have raised the demands of rigorous verification on safety-critical applications, which is unfortunately challenging for Simulink. In this paper, we present an approach to bridge the Stateflow based model driven development and a well- defined rigorous verification. First, we develop a self- contained toolkit to translate Stateflow model into timed automata, where major advanced modeling features in Stateflow are supported. Taking advantage of the strong verification capability of Uppaal, we can not only find bugs in Stateflow models which are missed by Simulink Design Verifier, but also check more important temporal properties. Next, we customize a runtime verifier for the generated nonintrusive VHDL and C code of Stateflow model for monitoring. The major strength of the customization is the flexibility to collect and analyze runtime properties with a pure software monitor, which opens more opportunities for engineers to achieve high reliability of the target system compared with the traditional act that only relies on Simulink Polyspace. We incorporate these two parts into original Stateflow based MDD seamlessly. In this way, safety-critical properties are both verified at the model level, and at the consistent system implementation level with physical execution environment in consideration. We apply our approach on a train controller design, and the verified implementation is tested and deployed on a real hardware platform.@eng bibo_authorlist: - foaf_Person: foaf_givenName: Yu foaf_name: Jiang, Yu foaf_surname: Jiang - foaf_Person: foaf_givenName: Yixiao foaf_name: Yang, Yixiao foaf_surname: Yang - foaf_Person: foaf_givenName: Han foaf_name: Liu, Han foaf_surname: Liu - foaf_Person: foaf_givenName: Hui foaf_name: Kong, Hui foaf_surname: Kong foaf_workInfoHomepage: http://www.librecat.org/personId=3BDE25AA-F248-11E8-B48F-1D18A9856A87 orcid: 0000-0002-3066-6941 - foaf_Person: foaf_givenName: Ming foaf_name: Gu, Ming foaf_surname: Gu - foaf_Person: foaf_givenName: Jiaguang foaf_name: Sun, Jiaguang foaf_surname: Sun - foaf_Person: foaf_givenName: Lui foaf_name: Sha, Lui foaf_surname: Sha bibo_doi: 10.1109/RTAS.2016.7461337 dct_date: 2016^xs_gYear dct_language: eng dct_publisher: IEEE@ dct_title: 'From stateflow simulation to verified implementation: A verification approach and a real-time train controller design@' ...