<?xml version="1.0" encoding="UTF-8"?>
<OAI-PMH xmlns="http://www.openarchives.org/OAI/2.0/"
         xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
         xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/ http://www.openarchives.org/OAI/2.0/OAI-PMH.xsd">
<ListRecords>
<oai_dc:dc xmlns="http://www.openarchives.org/OAI/2.0/oai_dc/"
           xmlns:oai_dc="http://www.openarchives.org/OAI/2.0/oai_dc/"
           xmlns:dc="http://purl.org/dc/elements/1.1/"
           xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
           xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/oai_dc/ http://www.openarchives.org/OAI/2.0/oai_dc.xsd">
   	<dc:title>A theory of register monitors</dc:title>
   	<dc:title>ACM/IEEE Symposium on Logic in Computer Science</dc:title>
   	<dc:creator>Ferrere, Thomas ; https://orcid.org/0000-0001-5199-3143</dc:creator>
   	<dc:creator>Henzinger, Thomas A ; https://orcid.org/0000−0002−2985−7724</dc:creator>
   	<dc:creator>Saraç, Ege</dc:creator>
   	<dc:description>The task of a monitor is to watch, at run-time, the execution of a reactive system, and signal the occurrence of a safety violation in the observed sequence of events. While finite-state monitors have been studied extensively, in practice, monitoring software also makes use of unbounded memory. We define a model of automata equipped with integer-valued registers which can execute only a bounded number of instructions between consecutive events, and thus can form the theoretical basis for the study of infinite-state monitors. We classify these register monitors according to the number k of available registers, and the type of register instructions. In stark contrast to the theory of computability for register machines, we prove that for every k 1, monitors with k + 1 counters (with instruction set 〈+1, =〉) are strictly more expressive than monitors with k counters. We also show that adder monitors (with instruction set 〈1, +, =〉) are strictly more expressive than counter monitors, but are complete for monitoring all computable safety -languages for k = 6. Real-time monitors are further required to signal the occurrence of a safety violation as soon as it occurs. The expressiveness hierarchy for counter monitors carries over to real-time monitors. We then show that 2 adders cannot simulate 3 counters in real-time. Finally, we show that real-time adder monitors with inequalities are as expressive as real-time Turing machines.</dc:description>
   	<dc:publisher>IEEE</dc:publisher>
   	<dc:date>2018</dc:date>
   	<dc:type>info:eu-repo/semantics/conferenceObject</dc:type>
   	<dc:type>doc-type:conferenceObject</dc:type>
   	<dc:type>text</dc:type>
   	<dc:type>http://purl.org/coar/resource_type/c_5794</dc:type>
   	<dc:identifier>https://research-explorer.ista.ac.at/record/144</dc:identifier>
   	<dc:source>Ferrere T, Henzinger TA, Saraç E. A theory of register monitors. In: Vol Part F138033. IEEE; 2018:394-403. doi:&lt;a href=&quot;https://doi.org/10.1145/3209108.3209194&quot;&gt;10.1145/3209108.3209194&lt;/a&gt;</dc:source>
   	<dc:language>eng</dc:language>
   	<dc:relation>info:eu-repo/semantics/altIdentifier/doi/10.1145/3209108.3209194</dc:relation>
   	<dc:relation>info:eu-repo/semantics/altIdentifier/wos/000545262800041</dc:relation>
   	<dc:rights>info:eu-repo/semantics/closedAccess</dc:rights>
</oai_dc:dc>
</ListRecords>
</OAI-PMH>
