{"_id":"144","date_created":"2018-12-11T11:44:52Z","publist_id":"7779","year":"2018","citation":{"ama":"Ferrere T, Henzinger TA, Saraç E. A theory of register monitors. In: Vol Part F138033. IEEE; 2018:394-403. doi:<a href=\"https://doi.org/10.1145/3209108.3209194\">10.1145/3209108.3209194</a>","ieee":"T. Ferrere, T. A. Henzinger, and E. Saraç, “A theory of register monitors,” presented at the LICS: Logic in Computer Science, Oxford, UK, 2018, vol. Part F138033, pp. 394–403.","mla":"Ferrere, Thomas, et al. <i>A Theory of Register Monitors</i>. Vol. Part F138033, IEEE, 2018, pp. 394–403, doi:<a href=\"https://doi.org/10.1145/3209108.3209194\">10.1145/3209108.3209194</a>.","ista":"Ferrere T, Henzinger TA, Saraç E. 2018. A theory of register monitors. LICS: Logic in Computer Science, ACM/IEEE Symposium on Logic in Computer Science, vol. Part F138033, 394–403.","chicago":"Ferrere, Thomas, Thomas A Henzinger, and Ege Saraç. “A Theory of Register Monitors,” Part F138033:394–403. IEEE, 2018. <a href=\"https://doi.org/10.1145/3209108.3209194\">https://doi.org/10.1145/3209108.3209194</a>.","apa":"Ferrere, T., Henzinger, T. A., &#38; Saraç, E. (2018). A theory of register monitors (Vol. Part F138033, pp. 394–403). Presented at the LICS: Logic in Computer Science, Oxford, UK: IEEE. <a href=\"https://doi.org/10.1145/3209108.3209194\">https://doi.org/10.1145/3209108.3209194</a>","short":"T. Ferrere, T.A. Henzinger, E. Saraç, in:, IEEE, 2018, pp. 394–403."},"type":"conference","conference":{"location":"Oxford, UK","end_date":"2018-07-12","start_date":"2018-07-09","name":"LICS: Logic in Computer Science"},"author":[{"first_name":"Thomas","last_name":"Ferrere","id":"40960E6E-F248-11E8-B48F-1D18A9856A87","orcid":"0000-0001-5199-3143","full_name":"Ferrere, Thomas"},{"full_name":"Henzinger, Thomas A","id":"40876CD8-F248-11E8-B48F-1D18A9856A87","orcid":"0000−0002−2985−7724","last_name":"Henzinger","first_name":"Thomas A"},{"first_name":"Ege","last_name":"Saraç","full_name":"Saraç, Ege"}],"language":[{"iso":"eng"}],"status":"public","department":[{"_id":"ToHe"}],"isi":1,"article_processing_charge":"No","date_published":"2018-07-09T00:00:00Z","abstract":[{"text":"The task of a monitor is to watch, at run-time, the execution of a reactive system, and signal the occurrence of a safety violation in the observed sequence of events. While finite-state monitors have been studied extensively, in practice, monitoring software also makes use of unbounded memory. We define a model of automata equipped with integer-valued registers which can execute only a bounded number of instructions between consecutive events, and thus can form the theoretical basis for the study of infinite-state monitors. We classify these register monitors according to the number k of available registers, and the type of register instructions. In stark contrast to the theory of computability for register machines, we prove that for every k 1, monitors with k + 1 counters (with instruction set 〈+1, =〉) are strictly more expressive than monitors with k counters. We also show that adder monitors (with instruction set 〈1, +, =〉) are strictly more expressive than counter monitors, but are complete for monitoring all computable safety -languages for k = 6. Real-time monitors are further required to signal the occurrence of a safety violation as soon as it occurs. The expressiveness hierarchy for counter monitors carries over to real-time monitors. We then show that 2 adders cannot simulate 3 counters in real-time. Finally, we show that real-time adder monitors with inequalities are as expressive as real-time Turing machines.","lang":"eng"}],"page":"394 - 403","publication_status":"published","month":"07","title":"A theory of register monitors","date_updated":"2023-09-08T11:49:13Z","quality_controlled":"1","publisher":"IEEE","external_id":{"isi":["000545262800041"]},"day":"09","oa_version":"None","volume":"Part F138033","user_id":"c635000d-4b10-11ee-a964-aac5a93f6ac1","alternative_title":["ACM/IEEE Symposium on Logic in Computer Science"],"doi":"10.1145/3209108.3209194","scopus_import":"1"}