{"date_updated":"2024-01-02T08:16:28Z","type":"conference","user_id":"2DF688A6-F248-11E8-B48F-1D18A9856A87","project":[{"_id":"fc2ed2f7-9c52-11eb-aca3-c01059dda49c","name":"IST-BRIDGE: International postdoctoral program","call_identifier":"H2020","grant_number":"101034413"},{"call_identifier":"H2020","grant_number":"101020093","name":"Vigilant Algorithmic Monitoring of Software","_id":"62781420-2b32-11ec-9570-8d9b63373d4d"}],"department":[{"_id":"ToHe"}],"oa_version":"Published Version","doi":"10.34727/2023/isbn.978-3-85448-060-0_20","ec_funded":1,"acknowledgement":"This work was supported by the European Union’s Horizon 2020 research and innovation programme under the Marie Skłodowska-Curie Grant Agreement No. 101034413 and the\r\n“VAMOS” grant ERC-2020-AdG 101020093.","file_date_updated":"2024-01-02T08:14:23Z","_id":"14718","file":[{"file_size":524321,"access_level":"open_access","creator":"dernst","success":1,"date_updated":"2024-01-02T08:14:23Z","date_created":"2024-01-02T08:14:23Z","checksum":"818d6e13dd508f3a04f0941081022e5d","file_name":"2023_FMCAD_Pastva.pdf","file_id":"14721","relation":"main_file","content_type":"application/pdf"}],"status":"public","conference":{"end_date":"2023-10-27","location":"Ames, IA, United States","start_date":"2023-10-25","name":"FMCAD: Conference on Formal Methods in Computer-aided design"},"publisher":"TU Vienna Academic Press","publication_status":"published","month":"10","date_created":"2023-12-31T23:01:03Z","publication":"Proceedings of the 23rd Conference on Formal Methods in Computer-Aided Design","tmp":{"name":"Creative Commons Attribution 4.0 International Public License (CC-BY 4.0)","legal_code_url":"https://creativecommons.org/licenses/by/4.0/legalcode","short":"CC BY (4.0)","image":"/images/cc_by.png"},"has_accepted_license":"1","publication_identifier":{"isbn":["9783854480600"]},"ddc":["000"],"title":"Binary decision diagrams on modern hardware","citation":{"ieee":"S. Pastva and T. A. Henzinger, “Binary decision diagrams on modern hardware,” in Proceedings of the 23rd Conference on Formal Methods in Computer-Aided Design, Ames, IA, United States, 2023, pp. 122–131.","short":"S. Pastva, T.A. Henzinger, in:, Proceedings of the 23rd Conference on Formal Methods in Computer-Aided Design, TU Vienna Academic Press, 2023, pp. 122–131.","chicago":"Pastva, Samuel, and Thomas A Henzinger. “Binary Decision Diagrams on Modern Hardware.” In Proceedings of the 23rd Conference on Formal Methods in Computer-Aided Design, 122–31. TU Vienna Academic Press, 2023. https://doi.org/10.34727/2023/isbn.978-3-85448-060-0_20.","ama":"Pastva S, Henzinger TA. Binary decision diagrams on modern hardware. In: Proceedings of the 23rd Conference on Formal Methods in Computer-Aided Design. TU Vienna Academic Press; 2023:122-131. doi:10.34727/2023/isbn.978-3-85448-060-0_20","apa":"Pastva, S., & Henzinger, T. A. (2023). Binary decision diagrams on modern hardware. In Proceedings of the 23rd Conference on Formal Methods in Computer-Aided Design (pp. 122–131). Ames, IA, United States: TU Vienna Academic Press. https://doi.org/10.34727/2023/isbn.978-3-85448-060-0_20","mla":"Pastva, Samuel, and Thomas A. Henzinger. “Binary Decision Diagrams on Modern Hardware.” Proceedings of the 23rd Conference on Formal Methods in Computer-Aided Design, TU Vienna Academic Press, 2023, pp. 122–31, doi:10.34727/2023/isbn.978-3-85448-060-0_20.","ista":"Pastva S, Henzinger TA. 2023. Binary decision diagrams on modern hardware. Proceedings of the 23rd Conference on Formal Methods in Computer-Aided Design. FMCAD: Conference on Formal Methods in Computer-aided design, 122–131."},"article_processing_charge":"No","scopus_import":"1","date_published":"2023-10-01T00:00:00Z","quality_controlled":"1","year":"2023","abstract":[{"text":"Binary decision diagrams (BDDs) are one of the fundamental data structures in formal methods and computer science in general. However, the performance of BDD-based algorithms greatly depends on memory latency due to the reliance on large hash tables and thus, by extension, on the speed of random memory access. This hinders the full utilisation of resources available on modern CPUs, since the absolute memory latency has not improved significantly for at least a decade. In this paper, we explore several implementation techniques that improve the performance of BDD manipulation either through enhanced memory locality or by partially eliminating random memory access. On a benchmark suite of 600+ BDDs derived from real-world applications, we demonstrate runtime that is comparable or better than parallelising the same operations on eight CPU cores. ","lang":"eng"}],"oa":1,"page":"122-131","author":[{"last_name":"Pastva","orcid":"0000-0003-1993-0331","first_name":"Samuel","id":"07c5ea74-f61c-11ec-a664-aa7c5d957b2b","full_name":"Pastva, Samuel"},{"id":"40876CD8-F248-11E8-B48F-1D18A9856A87","full_name":"Henzinger, Thomas A","orcid":"0000-0002-2985-7724","last_name":"Henzinger","first_name":"Thomas A"}],"language":[{"iso":"eng"}],"day":"01"}