{"quality_controlled":"1","year":"2024","date_published":"2024-02-01T00:00:00Z","ec_funded":1,"_id":"17053","title":"Ternary simulation as abstract interpretation (Work in Progress)","type":"conference","language":[{"iso":"eng"}],"month":"02","conference":{"name":"MBMV: Methods and Description Languages for Modeling and Verification of Circuits and Systems","end_date":"2024-02-15","start_date":"2024-02-14","location":"Kaiserslautern, Germany"},"citation":{"ieee":"N. Froleyks, Z. Yu, and A. Biere, “Ternary simulation as abstract interpretation (Work in Progress),” in <i>27th Workshop on Methods and Description Languages for Modeling and Verification of Circuits and Systems</i>, Kaiserslautern, Germany, pp. 148–151.","ista":"Froleyks N, Yu Z, Biere A. Ternary simulation as abstract interpretation (Work in Progress). 27th Workshop on Methods and Description Languages for Modeling and Verification of Circuits and Systems. MBMV: Methods and Description Languages for Modeling and Verification of Circuits and Systems, 148–151.","mla":"Froleyks, Nils, et al. “Ternary Simulation as Abstract Interpretation (Work in Progress).” <i>27th Workshop on Methods and Description Languages for Modeling and Verification of Circuits and Systems</i>, pp. 148–51.","apa":"Froleyks, N., Yu, Z., &#38; Biere, A. (n.d.). Ternary simulation as abstract interpretation (Work in Progress). In <i>27th Workshop on Methods and Description Languages for Modeling and Verification of Circuits and Systems</i> (pp. 148–151). Kaiserslautern, Germany.","ama":"Froleyks N, Yu Z, Biere A. Ternary simulation as abstract interpretation (Work in Progress). In: <i>27th Workshop on Methods and Description Languages for Modeling and Verification of Circuits and Systems</i>. ; :148-151.","short":"N. Froleyks, Z. Yu, A. Biere, in:, 27th Workshop on Methods and Description Languages for Modeling and Verification of Circuits and Systems, n.d., pp. 148–151.","chicago":"Froleyks, Nils, Zhengqi Yu, and Armin Biere. “Ternary Simulation as Abstract Interpretation (Work in Progress).” In <i>27th Workshop on Methods and Description Languages for Modeling and Verification of Circuits and Systems</i>, 148–51, n.d."},"date_updated":"2024-06-03T08:46:22Z","day":"01","status":"public","publication_status":"submitted","user_id":"2DF688A6-F248-11E8-B48F-1D18A9856A87","project":[{"_id":"62781420-2b32-11ec-9570-8d9b63373d4d","name":"Vigilant Algorithmic Monitoring of Software","grant_number":"101020093","call_identifier":"H2020"}],"article_processing_charge":"No","oa_version":"None","acknowledgement":"This work is supported by the Austrian Science Fund (FWF) under the project W1255-N23, the LIT AI Lab funded by the State of Upper Austria, the ERC-2020-AdG 101020093 and by a gift from Intel Corporation.","scopus_import":"1","date_created":"2024-05-26T22:00:58Z","department":[{"_id":"ToHe"}],"page":"148-151","abstract":[{"lang":"eng","text":"We introduce a formalization of ternary simulation as abstract interpretation along with a widening operator to speed up convergence. With the same goal, we present a subsumption algorithm that can determine termination earlier than the usual approach using hash sets. Additionally, we introduce a narrowing operator that utilizes recent advances in backbone extraction, allowing to increase the overapproximation precision in simulation at any time. The experiments evaluate the presented techniques in the context of hardware model checking."}],"author":[{"last_name":"Froleyks","full_name":"Froleyks, Nils","first_name":"Nils"},{"last_name":"Yu","id":"20aa2ae8-f2f1-11ed-bbfa-8205053f1342","full_name":"Yu, Zhengqi","first_name":"Zhengqi"},{"first_name":"Armin","full_name":"Biere, Armin","last_name":"Biere"}],"publication_identifier":{"isbn":["9783800762682"]},"publication":"27th Workshop on Methods and Description Languages for Modeling and Verification of Circuits and Systems"}