conference paper published yes Adrian Elgyütt author 4A2E9DBA-F248-11E8-B48F-1D18A9856A87 Thomas Ferrere author 40960E6E-F248-11E8-B48F-1D18A9856A870000-0001-5199-3143 Thomas A Henzinger author 40876CD8-F248-11E8-B48F-1D18A9856A870000−0002−2985−7724 ToHe department FORMATS: Formal Modeling and Analysis of Timed Systems Moderne Concurrency Paradigms project Formal methods for the design and analysis of complex systems project We solve the offline monitoring problem for timed propositional temporal logic (TPTL), interpreted over dense-time Boolean signals. The variant of TPTL we consider extends linear temporal logic (LTL) with clock variables and reset quantifiers, providing a mechanism to specify real-time constraints. We first describe a general monitoring algorithm based on an exhaustive computation of the set of satisfying clock assignments as a finite union of zones. We then propose a specialized monitoring algorithm for the one-variable case using a partition of the time domain based on the notion of region equivalence, whose complexity is linear in the length of the signal, thereby generalizing a known result regarding the monitoring of metric temporal logic (MTL). The region and zone representations of time constraints are known from timed automata verification and can also be used in the discrete-time case. Our prototype implementation appears to outperform previous discrete-time implementations of TPTL monitoring, https://research-explorer.ista.ac.at/download/81/8638/2018_LNCS_Elgyuett.pdf application/pdfno Springer2018Beijing, China eng 00088499320000410.1007/978-3-030-00151-3_4 1102253 - 70 Elgyütt A, Ferrere T, Henzinger TA. Monitoring temporal logic with clock variables. In: Vol 11022. Springer; 2018:53-70. doi:<a href="https://doi.org/10.1007/978-3-030-00151-3_4">10.1007/978-3-030-00151-3_4</a> Elgyütt, A., Ferrere, T., &#38; Henzinger, T. A. (2018). Monitoring temporal logic with clock variables (Vol. 11022, pp. 53–70). Presented at the FORMATS: Formal Modeling and Analysis of Timed Systems, Beijing, China: Springer. <a href="https://doi.org/10.1007/978-3-030-00151-3_4">https://doi.org/10.1007/978-3-030-00151-3_4</a> A. Elgyütt, T. Ferrere, T.A. Henzinger, in:, Springer, 2018, pp. 53–70. Elgyütt A, Ferrere T, Henzinger TA. 2018. Monitoring temporal logic with clock variables. FORMATS: Formal Modeling and Analysis of Timed Systems, LNCS, vol. 11022, 53–70. A. Elgyütt, T. Ferrere, and T. A. Henzinger, “Monitoring temporal logic with clock variables,” presented at the FORMATS: Formal Modeling and Analysis of Timed Systems, Beijing, China, 2018, vol. 11022, pp. 53–70. Elgyütt, Adrian, et al. <i>Monitoring Temporal Logic with Clock Variables</i>. Vol. 11022, Springer, 2018, pp. 53–70, doi:<a href="https://doi.org/10.1007/978-3-030-00151-3_4">10.1007/978-3-030-00151-3_4</a>. Elgyütt, Adrian, Thomas Ferrere, and Thomas A Henzinger. “Monitoring Temporal Logic with Clock Variables,” 11022:53–70. Springer, 2018. <a href="https://doi.org/10.1007/978-3-030-00151-3_4">https://doi.org/10.1007/978-3-030-00151-3_4</a>. 812018-12-11T11:44:31Z2025-04-15T06:26:03Z